Capacitors are a layout designer’s friend and sometimes nightmare.

For the purpose of this discussion, I will only focus on the most common device capacitor and that is the NMOS based gate type capacitor. It has a poly gate on N-Diff and contacts on both source and drain.

General Decoupling Caps (DCAPS) can be reshaped to fit irregular spaces but the more you pack them in it can be more difficult to run solid and regular connections to them from the intended power/gnd source.

A DCAP with a weak connection or too high of a resistance between source and drain is worthless in regards to performance, although it may be ok to fix density issues. The placement of such caps in nooks and crannies makes repairs to the layout more difficult. To be tasked with the installation of decoupling caps near the end of the project often requires some restraint from over exuberance.

When you have to do a project all by yourself, it is easier to set reasonable limitations on installing caps. You pick the high percentage areas and then come back to more detailed areas when you have that luxury after attending to more pressing matters.

Not all empty spaces are prime real estate for a decoupling cap. Especially near ESD where the haphazard placement of non ESD devices can cause problems. Putting noisy caps near a memory array or other sensitive low voltage circuit is also not good.

Although DCAP auto-fill routines can be great at packing an area with caps, the combination of irregular widths and lengths makes hookup a nightmare and is often a vomit worthy speed bump when it comes to efficient hookup.

The ideal implementation of a DCAP is one that shares a common source and drain pitch and has PTAPS built into them to avoid TAP low density issues and OD/POLY high density issues. This way interconnect layout that is used for hookup can be standardized and either facilitate hookup by repeated instances, groups or fixed array pitch to increase productivity and decrease frustration.

Placement of DCAPS as a process of filling in bulk areas should also leave more than minimum space from other active circuitry for general last minute routing to perform some mild engineering changes without having to alter DCAPS that are probably LVS and DRC clean at that point.

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MIXED Power Supply Considerations

If you are going to add DCAPS, you must collaborate with the circuit designers who have nightmares over unstable power supplies destroying the performance of their circuits. The layout designer will need to identify spaces and which spaces are idea for certain DCAPS. There are often multiple types of VDD and GNDs, containing varying degrees of inherent noise and they all need some help.

To be effective, the DCAP should be a close to the area that needs to be protected, not on the other side of the chip. ;(

It’s likely that the circuit designer will give you a preference, in regards to percentage use of the available spaces for which caps, just for example: 50% VDD/GND, 25% VCC/VSS and 25% VDDQ to GNDQ.

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CAPS in Power supplies, PUMPS, AMPS

Power supplies are loaded with capacitors, and we know that capacitors are flexible in how we can array them (adhering to any common central criteria when necessary), if not actually shaped them as as long as we end up with the correct total capacitance (more about capacitors in another post). These capacitors are often connected to nets other than VDD or GND, so extra care is in order in placing them effectively and to allow effective switching or options connections with adequate metal widths and isolation from nets that may cause noise coupling or mismatch issues.

Note: A layout designer should always get an “ok” from the circuit designer before decidingly altering any layout feature defined by a schematic. However, in your own initial planning on the layout side, you are usually free to “sketch out” anything to provide feedback to the circuit designer based on your discoveries in your layout.

In regards to memory, a good topography trick is to line the border of the memory array with the best DCAP (power/gnd combo) to isolate noise from the core. If one of the special power supply cells has a bunch of these caps already, consider making those part of the border/edge to do double duty. That may be a more effective use of space by distributing those caps.

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DCAPS in PLL or Timing or Sensitive Analog Circuits.

As in all matters related to sensitive timing circuits, the application of DCAPS should help promote the balance of inter-digitation or common central themes of many high speed or matching analog circuits. If caps are implemented around a PLL, for example, the entire topography around an Oscillator or other sensitive analog devices should promote matching borders in every possible direction adjacent to the circuit or that particular feature in the circuit.

Do not rely on auto-dummy or auto-capacitor fill to make up for density irregularities around sensitive circuits, this could be a good application for some custom drawn DCAPs which not only improve low density conditions but also add the benefit of stabilizing power and ground in a way that promotes good matching.

If you think it’s a good idea to add the DCAPS into the layout, see if the circuit designer is willing to add them into the schematic. He or she can always tell you “No.” If the circuit is repeated in other areas of the chip or is some kind of library cell, the answer will likely be “NO WAY!”

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HIGH FREQUENCY NOISE FILTER

Not every capacitor works best for every circuit. Long length capacitors are only capable of filtering low frequency noise. The higher the frequency that needs to be filtered out, the smaller the effective gate length needs to be. What that length is is best determined by the circuit designer.

Smaller length caps can filter both High and Low frequency noise, however, using a smaller length can significantly decrease the total area of your caps which is not good.

To check what the proper filtering properties are for your application are, please discuss this with your circuit design engineer.

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GUILTY Until Proven Innocent

You’ve heard of “Innocent until proven guilty.” When it comes to Layout that is going to be proliferated, it is UNCLEAN UNTIL PROVEN CLEAN.

Before mass proliferation of your DCAPS, whether custom installed or autofilled, please run verification on big arrays of your cap design before placing them en masse into the clean layout. It’s a good idea to place them in a unique layout instance so they can be removed easily for troubleshooting shorts.

After placement and before hookup is another good time to run verification and there after anytime you take a break or finish a significant part of the hookup. Yes, you should clean any errors when you find them especially if you tend to reuse your layout. Generally, you don’t want to reuse something that’s not DRC clean, it’ll just make more work for you later.

Not knowing if there are errors in the proliferated caps, whether custom or by autofill is bad. Do not assume it is clean within itself or to adjacent layouts. That’s not good for you if you need to get home on time – it’s a surprise you can do without (or for the other layout designer who needs to fix it).

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Go for a walk outside during the day, sunshine promotes the body’s vitamin D production.

Please like, share, follow, and/or comment. I would like to hear from you and if you have any non-NDA violating questions I can help answer.

CKY

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