One of the methods of creating layout that helps define a layout designer in making a transition to senior level is one of using bit-slice techniques to optimize the layout of a multi-bit pathway that often has multiple stages and internal metal bussing that if connected haphazardly would take up an enormous amount of space.

Unless the design is dogmatically based on the typical standard cells design which is used when space is not an issue or timing simulations are strictly tied to a given library and is usually not necessarily tolerant to alterations, the senior layout designer may opt to custom floorplan a layout in a “bit-slice” method.

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Possible Improvements using Bit-Splice layout:

1. Space usage
2. Interconnect and timing matching
3. Reduced interconnect RC and creation of “invisible” busing
4. Efficient power rail per row utilization
5. Simpler editing for ECO or optimizations
6. Pattern regularity of both active devices, guard bars, and power grid
7. Noise coupling improvements
8. Offers opportunity to share source nodes placement for further compaction
9. Offers easy stepped placement (idea for analog circuits) or alternating reflected (often okay for digital circuits).
10. Offers nested via connections (inside a repeated instance) for simpler connecting schemes.
11. Looks bad ass

The biggest difference between bit-slice and column or row pitch layout is bit slice is usually not slaved to a cell pitch (i.e. memory column or row pitch). It can be determined by space available or the optimal arrangement with respect to an existing bus output for a variety of blocks.

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Disadvantages

1. It becomes a macro so it is not standard cell friendly in terms of power pitch or portability.
2. For schematic == layout hierarchical LVS matching, it will require change in schematics to match layout configuration.
3. Increases in device sizes may increase total height of the bit-slice.
4. May not be sympathetic to your department or company’s back annotation strategy, since this block may require its own SIM models.

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Forgive my napkin-approved sketches, but here is an illustration of a generic schematic condition that may be idea for a bit slice treatment:

The number of strings would likely be the width (i.e. bus<31:0>, <63:0> etc.) of a large bus. Here in illustration 1, only 3 “bit strings” are shown. The typical standard cell style approach is where the device string running in the same direction as the base power bus (e.g. M1) whose direction is left to right. In other words, each row is assigned to a string.

A bit slice arrangement is like the following:

In a bit slice, each device that is similar to each string is arranged in their own M1 VDD/GND row. Local cell power are typically either M2 or M1 depending on your power grid plan and/or orientation of the bit-slice macro in relation to the power grid.

In other words, X4s are in their own row, X2s are in their own row, X1 latches are in their own row and the decode devices are on in their own row.

What you’ll discover is that each similar device is easier to optimize their space usage in each row (row height can vary to accommodate width of devices) but the designer should shoot to make the width of each stage identical, meaning the width of each stage should be so they stack in a neat column or pitch. This will make optimum use of space while nesting all the interconnect between stages inside each slice so instead of drawing 32 (or whatever the array number is) unique lines, you have 32 identical lines drawn once within each bit slice.

The larger buffers can be broken down in such a way that the width of the slice remains optimal through the altering the number of gate fingers (while maintaining the total buffer width) to accommodate the latch stage which tends to be less flexible in how it can be optimally constructed.

Although this style of layout is idea for many datapath layouts, you may also see similar schematic patterns in other circuits that may benefit for this kind of treatment.

Hope you got some value from this blurb on what I’ve called “bit slice” layout.

Please like, share, follow, and/or comment.

CKY

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