This is going to be really basic, but I want to go over it now for those of you who don’t have a practical understanding of gate proportions or why they are like the way they are.

I will only hit the explanation in a practical way without going in depth into manufacturing technology, so you process engineers can take a break.

Question: Why in a typical CMOS process is the Pgate larger than the Ngate?

In one word? Resistance

In a few more words: The PMOS and NMOS resistances are different and the PMOS is commonly higher, how much higher depends on the process.

In some extra words: In regards to the practical picture, in order to get an equivalent ‘strength’ from a PMOS, it needs to be drawn larger than an NMOS because the PMOS resistances are higher.

It’s a fallacy of new layout designers to think the PMOS is stronger because it’s “bigger”. Well, it’s not. It needs to be bigger because to get an equivalent effect it has more to overcome than its complementary NMOS gate.

Now I have seen processes where the PMOS/NMOS ratio is the same or ratios other than 2 to 1, but I’ll just say there are exceptions (from my experience).

For those of you who are sticking around for the senior level chat, for a little more advanced understanding, here it is.

To go into a little more in detail, the total resistance is the combination of not only the diffusion resistance but also the resistance of the transistor itself. The diffusion resistance for a hypothetical process may be, let’s say 100ohms per square and the activated transistor resistance may be 1000 ohms per square.

We can play with this condition in theory with practical layout applications in future posts.

Note: Check out the Electrical Rules when you study the DRCs and begin to get a practical understanding of how resistances can shape how you analyze and interpret the drawing in front of you. You can become more of a collaborator with the circuit designer rather than a only a first rate and sought for ‘polygon pusher’.

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CKY

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