For the majority of the first half of my career, I heard about PCELLs but never used them.

The companies I worked for had a basic version of the layout tool and a decent amount of in- house script support while creating databases without the use of PCELLs from the respective FABs. For better or worse, we just didn’t need those features and saved that money for other expenses.

With certain customers, we needed to adopt their methodology but those projects were not intended to port to multiple fabs.

We taped our most of our key projects out to several fabs using their CMOS logic processes and it was my responsibility to work with the Technologist and evaluate and QA “superset rules” for layout that would pass all the FAB rules with no or only minor, easy to implement adjustments.

The point of this article is to point out some particular detail of the layout methodology that I was responsible for. The methodology was GDS and cross-project friendly, meaning, we could stream data into a layout directory if needed to update a corrupted database or provide DRC or layout updates in general for any given project or any layout designer’s account assigned to a specific project.

CONTACT CELLS

I’m sure there’s other methodologies (I’m just one grain of sand on a beach) but given the available tools and other circumstances I was able to work with, I chose to create contact and via cells with the following features:

1. Origin point at the center of the hole, or if multi-hole, then at the center of the via array.
2. Includes connection layers drawn to DRC minimums or a compromise between FAB rulesets to make portability possible.
3. Typically only used square contact or vias even if a rectangular option was available.
4. Used a generic alpha-numeric system with the one letter prefix used as a FAB designator.
5. Create single and multiple hole configurations for each via layer, though contact was typically always a signal hole.
6. Provided common stacked via options.
7. Typically three sets of the contact cells were needed for a typical memory project (core, pitch, and periphery). They would all be placed into one official layout view for easy comparison.
8. As the layout manager, I reserved the right to maintain and edit these cells and to maintain their archive. If necessary, I would collaborate with the project leader if she needed an urgent update and needed to edit the contact set herself.
9. Each new layout account for a given project would include the correct set of contacts streamed into the specific directory because at the time we did not work out of central layout account. Updates would be done with stream with disciplined naming conventions to avoid conflicts between layout accounts.

One of the most important features is the location of the origin point because any biasing of the layers would have the least impact on a finished layout that would be ported to another FAB. This is an obvious consideration for VIAS placed on the center of bus lines. This also facilitates easier conversions between one via and another when the routing layers are shifted.

This also works well with source drain contacts that are placed in such a way that any adjustment needed for each FAB would not induce DRC errors (or very few) and smooth out the operation of porting from one FAB to the next.

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