So you’ve been tasked to create an IO pads with the ESD from scratch.

Just wanted you to understand some basics.

Rule Number One: Any NODE that is directly connected to the pad is subject to ESD damage and therefore must adhere to ESD rules. In other words, there needs to be some specially drawn ESD safety structures that directly interface to a bondpad connection. This applies to inputs and outputs. Today I’m focusing on the output.

Imagine an Electron of Mass Destruction (EMD) (FYI, this is a non-technical term) and when entering the bondpad, the EMD will seek the least path of resistance and exert all of your might there. Why? That’s by its nature, that’s what the Electron of Mass Destruction does, it seeks to create burnt toast.

If the EMD find a low resistance spot, it will heat that spot up. If that spot cannot handle the heat, that part of the layout will, in Star Trek lingo, “Cease to exist.”

For all practical purposes, any ESD will fry and die if exposed to a sustained level of voltage beyond its designed capacity. A conventional IOESD is only designed to handle momentary spikes in voltage like that which may be encountered in regular handling and assembly.

The concept behind ESD rules is to achieve an ESD structure to survive an ESD event and to do it in such a way that the EMD sees the same amount of protection everywhere it goes so it cannot exploit the weak link and fry the whole deal in a chain reaction. It’s a little bit like losing a section of heat shield on the space shuttle or a hole in a submarine. It doesn’t matter how strong everything else is, that one weakness becomes catastrophic.

Your job as a layout designer is to create a structure that:

1. Meets the minimum design rule for your technology’s ESD rules. Exceeding the minimum rules is possible and may be done in concert with the Technologist)
2. Make all points exposed to EMD’s identical as possible in terms of their ability to absorb the spikes in energy.
3. Follow all the ESD to non-ESD area spacing and guard ring requirements.
4. Ensure adequate and consistently applied power and ground structure the correct potentials (often IOESD will have its own power and ground due to the noisy nature of IO devices).
5. Understand the pitch criteria set forth in the floor planning of the IO PAD area. In other words, although there may be a minimum allowable pitch, you will need to confirm this. A package plan and a pin out plan are typically, or ought to be, settled before drawing of the IOESD in set forth in earnest. Otherwise, you will need to be flexible in how to floorplan the IOESD.

The DRC/ESD/IO rules will usually specify the minimum gate width requirement to achieve the industry standard ESD voltage requirement, for instance, a spike of a certain number of volts in the thousands ( I recall 4K being one spec).

From this baseline, you can derive the number of those devices to be used as part of your P and N drivers as defined in the IO circuit schematic. In case you didn’t get this earlier, yes, the output drivers and any optional output drivers in the schematic are going to use the devices that must be drawn to ESD specs, NOT to standard logic DRC rules (I can go over this more in detail later if you are interested).

Consequently, the ideal ESD takes into consideration the total ESD width and output buffer size and from those two is derived one layout device that is array able so that all the fingers of the IO/ESD structure are identical, including the same gate width. The circuit designer can help in this case, since he usually has some margin to make adjustments to make your effort to make everything symmetrical possible. Nevertheless, the ideal is not always easily implemented and the first order, along with meeting the ESD rules is to floorplan the IOESD to conserve space, in other words, the N and P channels are proportioned to fit efficiently into the given pitch.

Some characteristics to note of the ESD rules for gates are (not in any particular order):

1. Very conservative contact to gate space on the Drain side (the side that is connected to the bondpad.
2. A larger than normal gate length.
3. A large than normal space contact to gate on the source side but not like on bondpad connection.
4. The space from the drain contact to the edge of the OD can be an issue and the rule may be the same as contact to gate for the drain. Refer to your ESD rules.
5. Use of special layers may apply to make the gate or contact areas more resistance to ESD damage.

Broaching another subject, but related:

IO/ESD floor planning configurations are optimized depending on the chip, pad ring floorplan. The top level or ring level floorplan, in conjunction with package considerations, is critical. The project lead must have to have a clear picture of the chip/package plan of before the ESD/Pad cell configuration can be determined. See illustration below for examples on the chip side.

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Health Note: One of the worst things I did for my health as a layout designer was make good use of the free cans of soda in the break room. Along with adding a lot of sugars and artificial sweeteners to your body, sodas interfere with the absorption of minerals, especially calcium. Adverse long term effects are diabetes, kidney stones, and brittle bones.

Fortunately, I stopped before getting into long term effects but know others that have had to suffer.

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CKY

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