If you are stuck without the capabilities of having PCELLS or you choose to create your own library cells to support custom layout as part of your methodology, that is the situation that I found myself in for a good part of the first half of my 33 years in the industry. The following are some ideas for establishing a set of cells used in a project custom reference library (PCRL) that may ideally be used by all designers involved in the project to improve consistency and adaptabilities to the layout across the project.

The library would include not only the MOS devices but also a standard interconnect and VDD and GND rails, in this way, the PCRL can bridge the gap between what we commonly see nowadays as schematic driven placement and interconnect. The value seen in a completed PCRL is the consistency of layout similar to a robust standard cell design (drawn to higher yield and ease of editing, and not drawn to FAB specs which commonly are prohibited), with the flexibility to adjust given the floorplan, bit slice type requirements, or need for compaction.

The Gate

One feature that I found helpful was to draw each gate as a rectangle, unmerged with any interconnect poly. This feature should be maintained throughout the project.

Use the most conservative gate extension among the design rules that the superset is designed for.

I used a rectangle and not a path. I’ve never seen a gate drawn as a path, but that’s just my perspective. A path has limitations in regards to its ability to bias on-grid and, although I would use a conservative gate extension, it’s harder to define the gate extension to be manipulated by script or GUI for a path because that is contrary to its sizable feature.

I placed the gate centered between the source and drain contacts and if there was any limitations in centering it, it would be biased towards the drain contact(s) to reduce the drain capacitance (albeit ever so slightly). This would be an initial placement which could be adjusted depending on the usage.

Generally speaking in a logic cell layout, any slop area that occurs in the drain should be adjusted to meet the project’s rules for drain contact to gate spacing in effort to reduce capacitance on the drain. The project rules must consider any planned chip or block level manipulations so that DRC errors do not occur. Even with the highly customized layout, the primary focus should be to minimize the back end work needed to proliferate the database.

There may be certain sections of layout (i.e. the FAB’s IP macros) that will be designed specifically for a given FAB, so naturally, generic project rules will not apply to them.

There will be other gate to contact considerations for DRC guidelines for ESD or certain analog layout.

By using a rectangle, the layout database can be more easily manipulated by scripts (which would be best, especially when the bias direction can be defined as only towards the source and drain) and they can also be edited en-masse using the global commands in the GUI or by manual selection of an edge(s) with the editor.

I’ll share some ideas about the contact and gate relationship in near future articles in regards this example of a highly custom manipulated layout database, which we will further see how discipline is required to not merge the rectangles (much like PCELLS are unique per gate).

Merging rectangles into one clean looking POLY layer polygon can be an inclination but should be avoided using this kind of methodology to maintain individual rectangle control of each gate. In other words, it’s better to keep rectangles that define LVS parameters so they can be altered using height or width properties which do not exist in a non-rectangle polygon.

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CKY

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