IC Layout

Integrated Circuit Layout Design

Challen Yee AMS Layout Engineer

ICL 23.26 Analog Concepts – DAC

In the creation of high performance DACs for video outputs, speed is a consideration but the ability to have matching and accurate performance is critical.

Some guidelines provided in this post are not applicable to all technologies; however, they can be used as a guideline in principle in regards to analog matching with the presumption of moderating variations that can effect parasitics due to manufacturing variation.

Principle/Guideline: Minimum rules may allow for the most compact layout but NOT for improved matching.

This principle can be applied to multiple areas of the layout such as:

  1. Gate, space, width and length
  2. Contact to contact spacing
  3. Contact to Gate spacing
  4. OD extension over Contact
  5. Gate Extensions
  6. Poly overlap of Contact
  7. Poly interconnect space to OD
  8. Metal overlap of Contact
  9. Implant overlap of OD and poly
  10. NWELL Overlap
  11. Metal width and spacing.
  12. Tap spacing/Guard ring enclosures
  13. Liberal use of dummy structures and consistent borders guard rings, DCAPS, to enhance edge matching and reducing noise interference to bias signals.
  14. Missing anything? I’m sure we could dig up more ways to enhance matching.

As a general guideline, when there are no recommended rules, you (“you” meaning in concert with the resident technologists) can establish your own “recommended” rules.

If possible, you can start with a 10% overage of the minimum rules. Some of these overages can also help implement a greater multi-fab capable database by being able to meet several FAB rules with only a minor manipulation of the database. Naturally, more restrictive technologies will not allow for as much flexibility.

ICL ILLUSTRATION 1: DAC OUTPUT with ESD CONSIDERATIONS, X = ?

I’d like to highlight the contact to contact spacing and OD overlap of contact that further decrease the possibility of bridging between contacts and reduce the influence of resistance variations introduced by the OD edge and bird’s beak on the outer contacts.

As a matter of pad ESD rules, the drain of a DAC may require or be subject to special rules that, given the enormity of the DAC output area, may not be as conservative as the standard ESD rules. Special considerations for ESD may be offered due to a large area of a DAC output. Any space savings in this area will offer dramatic area use reductions.

As always, DRC rules need to be met. Exceptions can be granted if the FAB, resident technologist and engineering agree.

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CKY

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2 responses to “ICL 23.26 Analog Concepts – DAC”

  1. Hi CKY,
    I like your approach of having 10% extra margin for future node migration. That’s a great oversight to have. Usually due to our hectic schedule, we try to close the layout and get ready for the tapeout ASAP. But you are right, if we have this insight it will help us in the future as well.

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    1. Hi ARK,
      You’re right, though it would take a clearer picture of the actual roadmap and some consideration which way to go in regards to layout drawn more conservatively. However, the increased dimensions have an effect on the matching ability of the analog layout and would be less of a migrations move and more of a performance decision. In either case, Usually teams go with the defaults in the PDK and don’t mess with it, the net results are smallest layout side, but with a executive level plan, could still implement an overage if it can save time on multiple projects.

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