Every circuit is subject to change but random logic control blocks have a special place in my heart. I’m talking about the ones that had to be printed out on a couple of pages in order to see the whole block while the device details were barely large enough to read the sizes.

What was a benefit (in my circumstances) in those days before the interactive type schematic/layout suites was that the engineer had to run all of this net connection by hand and the layout designer could get a handle on the wire “flights” by just looking instead of reading unintuitive schematic virtual connections. Highlighters were a popular tool to mark up schematics.

Yes, you are right, most circuit designers will say running all those lines was absolutely NOT an benefit.

In the early stages of the company, I would be willing to assemble random logic control blocks without the use of an APR tool. We didn’t afford the licenses. All I can say is, fortunately these control block schematics were not larger than they were, though they were manageable, in my opinion, they were also pretty complex.

Nevertheless, the necessity of it being a full custom layout design, was good practice in identifying patterns in the schematics which were exploitable to guide floor planning.

Although we did not use an APR tool, I still had the discipline of creating a “standard” cell library for these kind of custom layout assignments. The standard cell had all the PCRL (personal custom reference library) type enhancements ( mask change ability, ECO friendly, multi-FAB ability…. all the things that a minimized std lib does not offer as well), including a robust M2 power scheme that made connecting the block easier to meet EMIR requirements.

Eventually I was able to help other layout designer(s) to take on this responsibility and it was always a great assignment to have discussions over.

Nothing like bonding over a common pain point (LOL) but it’s important to convey insights and prove it can be done efficiently leveraging the tools that we had available.

The real pain often does not come with the initial planning, it comes with the changes that come afterwards. Being random logic, there’s little in regards to repeatable routing or ability to bit-slice. The heart of the circuit was often a series of counters, but this was only a small consolation.

The point of this article has more to do with understanding the volatility of a given schematic (its propensity for being changed) and also the nature of the circuit designer in charge of the design.

While it is a good idea to prepare visualizing the layout in the process of floor planning, in the beginning, you might elect to go all out getting the block done.

Sometimes getting a block “done” is not the best time management tip.

I am sure I surprised the circuit designer several times by completing the block quickly, maybe 3 days, he would surprise me with a greater change than I would have expected and the change would take a significant amount of time to implement.

Changes in this case, are always more difficult to make than when drawing from scratch. The only advantage at this point is you have become very familiar with the schematics and it is no longer “random”, meaning you can see how the various groups of cells you created give definition to the block as well as have intimate familiarity with critical lines.

Sometimes… when the circuit designer says the simulations “look good”, that could be translated to something as certain as guessing the best stock pick for the next two years. Depending on which designer is producing the schematics, you might ask a few more questions about the progress of his or her simulations and then place your own developing understanding of what “look good” really means.

If you are sane, then that kind of experience should cause some restraint on ones willingness to “finish” the layout. You could do something else that requires your attention that is more stable – in other words, it becomes a time management issue. If you a project leader, you need to understand this dynamic if you delegate this kind of assignment.

In general, though, random logic control blocks, if they are a new design on their first implementation, are subject to a high degree of volatility.

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As we get into the Christmas holiday season, I will be reducing the frequency of my posts.

Speaking of Christmas gifts, have you ever received any notable gifts from the company? I still use a nice coffee mug I received from one of my managers.

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CKY

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